(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a narrow polysilicon gate or other small feature size structures using i-line photolithography in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, photolithography and etching are used to form structures such as polysilicon gates, word lines, bit lines, local oxidation of silicon (LOCOS), shallow trench isolation (STI), and the like. A photoresist material is coated over the layer or layers to be etched. The photoresist material is exposed to actinic light through a mask, then developed to form the photoresist mask for etching the underlying layer or layers. Small feature sizes, on the order of 0.1 to 0.35 microns, are not resolved easily by i-line photolithography.
U.S. Pat. No. 5,597,764 To Koh et al teaches a method of etching contact openings smaller than the openings in a photoresist mask by partially etching into the underlying layer, then depositing an oxide layer within the partially etched openings to decrease the size of the openings. A second etch extends the smaller openings through to the underlying layer to be contacted. U.S. Pat. No. 5,013,398 to Long et al teaches an anisotropic etch method for an oxide/polysilicon structure. U.S. Pat. No. 4,414,057 to Bourassa et al teaches an anisotropic etch method for silicide/polysilicon.